575 search results - page 29 / 115 » Computing Maximum Subsequence in Parallel |
IPPS
2008
IEEE
14 years 2 months ago
2008
IEEE
In this work we examine the implications of building a single logical link out of multiple physical links. We use MultiEdge [12] to examine the throughput-CPU utilization tradeoff...
ICPP
2003
IEEE
14 years 26 days ago
2003
IEEE
A hardware-assisted design, dubbed cache-oriented multistage structure (COMS), is proposed for fast packet forwarding. COMS incorporates small on-chip cache memory in its constitu...
ICCS
2009
Springer
13 years 5 months ago
2009
Springer
Abstract. The efficient use of multicore architectures for sparse matrixvector multiplication (SpMV) is currently an open challenge. One algorithm which makes use of SpMV is the ma...
IPPS
1998
IEEE
13 years 12 months ago
1998
IEEE
In this abstract, we provide an overview of our survey of randomized techniques for exploiting the parallelism in string matching problems. Broadly, the study of string matching fa...
IPPS
2010
IEEE
13 years 5 months ago
2010
IEEE
Peta-scale scientific applications running on High End Computing (HEC) platforms can generate large volumes of data. For high performance storage and in order to be useful to scien...