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» Computing in the Presence of Timing Failures
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GLVLSI
2006
IEEE
143views VLSI» more  GLVLSI 2006»
14 years 1 months ago
SACI: statistical static timing analysis of coupled interconnects
Process technology and environment-induced variability of gates and wires in VLSI circuits make timing analyses of such circuits a challenging task. Process variation can have a s...
Hanif Fatemi, Soroush Abbaspour, Massoud Pedram, A...
RTSS
2003
IEEE
14 years 1 months ago
Adaptive Coherency Maintenance Techniques for Time-Varying Data
Often, data used in on-line decision making (for example, in determining how to react to changes in process behavior, traffic flow control, etc.) is dynamic in nature and hence ...
Ratul kr. Majumdar, Kannan M. Moudgalya, Krithi Ra...
RTSS
2003
IEEE
14 years 1 months ago
Data Caches in Multitasking Hard Real-Time Systems
Data caches are essential in modern processors, bridging the widening gap between main memory and processor speeds. However, they yield very complex performance models, which make...
Xavier Vera, Björn Lisper, Jingling Xue
RTSS
2006
IEEE
14 years 1 months ago
Mutual Consistency in Real-Time Databases
A real-time database is composed of real-time objects whose values remain valid only within their validity intervals. Each object in the database models a real world entity. The f...
Abhay Kumar Jha, Ming Xiong, Krithi Ramamritham
CADE
2006
Springer
14 years 8 months ago
CEL - A Polynomial-Time Reasoner for Life Science Ontologies
CEL (Classifier for EL) is a reasoner for the small description logic EL+ which can be used to compute the subsumption hierarchy induced by EL+ ontologies. The most distinguishing ...
Franz Baader, Carsten Lutz, Boontawee Suntisrivara...