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MICRO
2010
IEEE
140views Hardware» more  MICRO 2010»
13 years 5 months ago
STEM: Spatiotemporal Management of Capacity for Intra-core Last Level Caches
Efficient management of last level caches (LLCs) plays an important role in bridging the performance gap between processor cores and main memory. This paper is motivated by two key...
Dongyuan Zhan, Hong Jiang, Sharad C. Seth
WWW
2003
ACM
14 years 8 months ago
Buffer Sharing for Proxy Caching of Streaming Sessions
With the falling price of the memory, an increasing number of multimedia servers and proxies are now equipped with a large memory space. Caching media objects in the memory of a p...
Songqing Chen, Bo Shen, Yong Yan, Xiaodong Zhang
SSS
2010
Springer
128views Control Systems» more  SSS 2010»
13 years 6 months ago
On Transactional Scheduling in Distributed Transactional Memory Systems
We present a distributed transactional memory (TM) scheduler called Bi-interval that optimizes the execution order of transactional operations to minimize conflicts. Bi-interval c...
Junwhan Kim, Binoy Ravindran
DAMON
2007
Springer
14 years 1 months ago
Parallel buffers for chip multiprocessors
Chip multiprocessors (CMPs) present new opportunities for improving database performance on large queries. Because CMPs often share execution, cache, or bandwidth resources among ...
John Cieslewicz, Kenneth A. Ross, Ioannis Giannaka...
ICPADS
2007
IEEE
14 years 2 months ago
Persistence and communication state transfer in an asynchronous pipe mechanism
Abstract— Emergent wide-area distributed systems like computational grids present opportunities for large scientific applications. On these systems, communication mechanisms hav...
Philip Chan, David Abramson