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» Configurable Transactional Memory
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PLDI
2012
ACM
11 years 11 months ago
JANUS: exploiting parallelism via hindsight
This paper addresses the problem of reducing unnecessary conflicts in optimistic synchronization. Optimistic synchronization must ensure that any two concurrently executing trans...
Omer Tripp, Roman Manevich, John Field, Mooly Sagi...
GLVLSI
2008
IEEE
137views VLSI» more  GLVLSI 2008»
14 years 3 months ago
Phase-based cache reconfiguration for a highly-configurable two-level cache hierarchy
Phase-based tuning methodologies specialize system parameters for each application phase of execution. Parameters are varied during execution, as opposed to remaining fixed as in ...
Ann Gordon-Ross, Jeremy Lau, Brad Calder
JRTIP
2008
249views more  JRTIP 2008»
13 years 8 months ago
Model-based mapping of reconfigurable image registration on FPGA platforms
Abstract Image registration is a computationally intensive application in the medical imaging domain that places stringent requirements on performance and memory management efficie...
Mainak Sen, Yashwanth Hemaraj, William Plishker, R...
HPCA
2002
IEEE
14 years 9 months ago
The Minimax Cache: An Energy-Efficient Framework for Media Processors
This work is based on our philosophy of providing interlayer system-level power awareness in computing systems [26, 27]. Here, we couple this approach with our vision of multipart...
Osman S. Unsal, Israel Koren, C. Mani Krishna, Csa...
MICRO
2010
IEEE
172views Hardware» more  MICRO 2010»
13 years 6 months ago
Architectural Support for Fair Reader-Writer Locking
Abstract--Many shared-memory parallel systems use lockbased synchronization mechanisms to provide mutual exclusion or reader-writer access to memory locations. Software locks are i...
Enrique Vallejo, Ramón Beivide, Adriá...