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CORR
2010
Springer
94views Education» more  CORR 2010»
13 years 7 months ago
Unidirectional Error Correcting Codes for Memory Systems: A Comparative Study
In order to achieve fault tolerance, highly reliable system often require the ability to detect errors as soon as they occur and prevent the speared of erroneous information throu...
Muzhir Al-Ani, Qeethara Al-Shayea
CHI
2006
ACM
14 years 8 months ago
Designing for collective remembering
This paper outlines the rationale for the workshop topic and offers an overview of its objectives. Keywords Collective memories, episodic memory, memory technology, interaction de...
Corina Sas, Alan J. Dix
ISCAS
2003
IEEE
78views Hardware» more  ISCAS 2003»
14 years 28 days ago
History-based memory mode prediction for improving memory performance
To increase the bandwidth of synchronous memories that are widely adopted for high performance memory systems, a predictive mode control scheme is proposed to reduce memory latenc...
Seong-Il Park, In-Cheol Park
CDES
2008
166views Hardware» more  CDES 2008»
13 years 9 months ago
Scalable Directory Organization for Tiled CMP Architectures
Although directory-based cache coherence protocols are the best choice when designing chip multiprocessor architectures (CMPs) with tens of processor cores on chip, the memory ove...
Alberto Ros, Manuel E. Acacio, José M. Garc...
ICDCSW
2003
IEEE
14 years 28 days ago
Broadcast Data Organizations and Client Side Cache
Broadcasting provides an e cient means for disseminating information in both wired and wireless setting. In this paper, we study di erent client side cache organizations for vario...
Oleg Shigiltchoff, Panos K. Chrysanthis, Evaggelia...