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CAL
2008
13 years 7 months ago
Hierarchical Instruction Register Organization
This paper analyzes a range of architectures for efficient delivery of VLIW instructions for embedded media kernels. The analysis takes an efficient Filter Cache as a baseline and ...
David Black-Schaffer, James D. Balfour, William J....
DATE
2007
IEEE
99views Hardware» more  DATE 2007»
14 years 2 months ago
Very wide register: an asymmetric register file organization for low power embedded processors
In current embedded systems processors, multi-ported register files are one of the most power hungry parts of the processor, even when they are clustered. This paper presents a n...
Praveen Raghavan, Andy Lambrechts, Murali Jayapala...
VLSID
2001
IEEE
118views VLSI» more  VLSID 2001»
14 years 8 months ago
Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language
Memory represents a major bottleneck in modern embedded systems. Traditionally, memory organizationsfor programmable systems assumed a fixed cache hierarchy. Withthe wideningproce...
Prabhat Mishra, Peter Grun, Nikil D. Dutt, Alexand...
PUC
2007
238views more  PUC 2007»
13 years 7 months ago
Ubiquitous Memories: a memory externalization system using physical objects
In this paper we propose an object-triggered human memory augmentation system named ‘‘Ubiquitous Memories’’ that enables a user to directly associate his/her experience dat...
Tatsuyuki Kawamura, Tomohiro Fukuhara, Hideaki Tak...
ADBIS
2004
Springer
134views Database» more  ADBIS 2004»
14 years 1 months ago
Towards Quadtree-Based Moving Objects Databases
Nowadays, one of the main research issues of great interest is the efficient tracking of mobile objects that enables the effective answering of spatiotemporal queries. This line o...
Katerina Raptopoulou, Michael Vassilakopoulos, Yan...