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» Constraint Hierarchies and Logic Programming
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NMR
2004
Springer
14 years 1 months ago
Frame consistency: computing with causal explanations
This paper presents a computational model for reasoning with causal explanations of observations within the framework of Abductive Event Calculus (AEC). The model is based on abdu...
Andrea Bracciali, Antonis C. Kakas
CP
2006
Springer
13 years 11 months ago
Stochastic Allocation and Scheduling for Conditional Task Graphs in MPSoCs
This paper describes a complete and efficient solution to the stochastic allocation and scheduling for Multi-Processor System-on-Chip (MPSoC). Given a conditional task graph charac...
Michele Lombardi, Michela Milano
CAV
2004
Springer
151views Hardware» more  CAV 2004»
13 years 11 months ago
QB or Not QB: An Efficient Execution Verification Tool for Memory Orderings
We study the problem of formally verifying shared memory multiprocessor executions against memory consistency models--an important step during post-silicon verification of multipro...
Ganesh Gopalakrishnan, Yue Yang, Hemanthkumar Siva...
GPCE
2008
Springer
13 years 8 months ago
Property models: from incidental algorithms to reusable components
A user interface, such as a dialog, assists a user in synthesising a set of values, typically parameters for a command object. Code for “command parameter synthesis” is usuall...
Jaakko Järvi, Mat Marcus, Sean Parent, John F...
PATMOS
2007
Springer
14 years 1 months ago
Soft Error-Aware Power Optimization Using Gate Sizing
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Ma...