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» Constraint-driven communication synthesis
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ISCAS
2008
IEEE
109views Hardware» more  ISCAS 2008»
14 years 2 months ago
A dual-core programmable decoder for LDPC convolutional codes
Abstract— We present the concepts and realization of a highly parallelized decoder architecture for LDPC convolutional codes and tailbiting LDPC convolutional codes. This archite...
Marcos B. S. Tavares, Emil Matús, Steffen K...
ICCAD
1995
IEEE
77views Hardware» more  ICCAD 1995»
13 years 11 months ago
PARAS: system-level concurrent partitioning and scheduling
Partitioning for the ASIC designs is examined and the interaction between high-level synthesis and partitioning is studied and incorporated in the solution. Four algorithms (calle...
Wing Hang Wong, Rajiv Jain
DISCEX
2003
IEEE
14 years 1 months ago
Willow System Demonstration
Dealing with damage that arises during operation of networked information systems is essential if such systems are to provide the dependability required by modern critical applica...
John C. Knight, Jonathan Hill, Philip E. Varner, P...
ICC
2007
IEEE
102views Communications» more  ICC 2007»
14 years 2 months ago
A Scalable Wireless Channel Emulator for Broadband MIMO Systems
: This paper addresses the issue of designing scalable prototypes for multi input multi output (MIMO) wireless channel emulation. To date, emulators are extending single input sing...
Hamid Eslami, Ahmed M. Eltawil
EUROPAR
2001
Springer
14 years 8 days ago
Multiprocessor Clustering for Embedded Systems
Abstract. In this paper, we address two key trends in the synthesis of implementations for embedded multiprocessors — (1) the increasing importance of managing interprocessor com...
Vida Kianzad, Shuvra S. Bhattacharyya