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ISCA
2006
IEEE
162views Hardware» more  ISCA 2006»
16 years 21 hour ago
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communicati...
Feihui Li, Chrysostomos Nicopoulos, Thomas D. Rich...
RTSS
2006
IEEE
16 years 11 hour ago
Tightening the Bounds on Feasible Preemption Points
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
Harini Ramaprasad, Frank Mueller
ACISP
2006
Springer
15 years 12 months ago
On Exact Algebraic [Non-]Immunity of S-Boxes Based on Power Functions
In this paper we are interested in algebraic immunity of several well known highly-nonlinear vectorial Boolean functions (or Sboxes), designed for block and stream ciphers. Unfortu...
Nicolas Courtois, Blandine Debraize, Eric Garrido
RTAS
2005
IEEE
15 years 11 months ago
Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns
While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and partic...
Harini Ramaprasad, Frank Mueller
CCS
2005
ACM
15 years 11 months ago
A rewriting-based inference system for the NRL protocol analyzer: grammar generation
The NRL Protocol Analyzer (NPA) is a tool for the formal specification and analysis of cryptographic protocols that has been used with great effect on a number of complex real-l...
Santiago Escobar, Catherine Meadows, José M...