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» Control Generation for Logic Programs
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CODES
2008
IEEE
13 years 10 months ago
Model checking SystemC designs using timed automata
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...
Paula Herber, Joachim Fellmuth, Sabine Glesner
ICFP
2005
ACM
14 years 8 months ago
Modular verification of concurrent assembly code with dynamic thread creation and termination
Proof-carrying code (PCC) is a general framework that can, in principle, verify safety properties of arbitrary machine-language programs. Existing PCC systems and typed assembly l...
Xinyu Feng, Zhong Shao
SAC
2010
ACM
13 years 10 months ago
Reactive parallel processing for synchronous dataflow
The control flow of common processors does not match the specific needs of reactive systems. Key issues for these systems are preemption and concurrency, combined with timing pred...
Claus Traulsen, Reinhard von Hanxleden
TLDI
2005
ACM
102views Formal Methods» more  TLDI 2005»
14 years 1 months ago
An open and shut typecase
Two different ways of defining ad-hoc polymorphic operations commonly occur in programming languages. With the first form polymorphic operations are defined inductively on the...
Dimitrios Vytiniotis, Geoffrey Washburn, Stephanie...
GECCO
2009
Springer
163views Optimization» more  GECCO 2009»
14 years 2 months ago
Dealing with inheritance in OO evolutionary testing
Most of the software developed in the world follows the object-oriented (OO) paradigm. However, the existing work on evolutionary testing is mainly targeted to procedural language...
Javier Ferrer, J. Francisco Chicano, Enrique Alba