141 search results - page 4 / 29 » Core Algorithms of the Maui Scheduler |
DELTA
2004
IEEE
13 years 11 months ago
2004
IEEE
Manufacturing test of chips made of multiple IP cores requires different techniques if ATE is used. As scan chains are commonly used as access paths to the DUT, ATE architectures ...
CN
2008
13 years 8 months ago
2008
Electrical-to-optical domain conversions and vice versa (denoted by O/E/O conversions) for each hop in optical core transport networks impose considerable capital and financial ov...
ISCA
2012
IEEE
11 years 10 months ago
2012
IEEE
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from t...
TOG
2012
11 years 10 months ago
2012
Using existing programming tools, writing high-performance image processing code requires sacrificing readability, portability, and modularity. We argue that this is a consequenc...
NOSSDAV
2004
Springer
14 years 1 months ago
2004
Springer
Despite many years of research, fair queuing still faces a number of implementation challenges in high speed routers. In particular, in spite of proposals such as DiffServ, the st...