275 search results - page 36 / 55 » Core architecture optimization for heterogeneous chip multip... |
ICS
2005
Tsinghua U.
14 years 2 months ago
2005
Tsinghua U.
As network traffic continues to increase and with the requirement to process packets at line rates, high performance routers need to forward millions of packets every second. Eve...
ITNG
2008
IEEE
14 years 3 months ago
2008
IEEE
This paper presents several parallel FFT algorithms with different degree of communication overhead for multiprocessors in Network-on-Chip(NoC) environment. Three different method...
RTSS
2006
IEEE
14 years 2 months ago
2006
IEEE
Modern FPGA devices, which include (multiple) processor core(s) as diffused IP on the silicon die, provide an excellent platform for developing custom multiprocessor systems-on-pr...
JSA
2010
13 years 3 months ago
2010
During the past few years, embedded digital systems have been requested to provide a huge amount of processing power and functionality. A very likely foreseeable step to pursue th...
FPL
2008
Springer
13 years 10 months ago
2008
Springer
This paper investigates reconfigurable architectures suitable for chip multiprocessors (CMPs). Prior research has established that augmenting a conventional processor with reconfi...