275 search results - page 42 / 55 » Core architecture optimization for heterogeneous chip multip... |
ICS
2010
Tsinghua U.
13 years 11 months ago
2010
Tsinghua U.
The growing influence of wire delay in cache design has meant that access latencies to last-level cache banks are no longer constant. Non-Uniform Cache Architectures (NUCAs) have ...
IPPS
2007
IEEE
14 years 2 months ago
2007
IEEE
Emerging heterogeneous multiprocessors will have custom memory and bus architectures that must balance resource sharing and system partitioning to meet cost constraints. We propos...
HPCA
2009
IEEE
14 years 9 months ago
2009
IEEE
Magnetic Random Access Memory (MRAM) is considered to be a promising future memory technology due to its low leakage power, high density and fast read speed. The heterogeneous int...
EUC
2005
Springer
14 years 2 months ago
2005
Springer
We propose an efficient scheme called CoReS (Configuration and Registration Scheme) that integrates address assignment and service location for ad hoc networks prevalent in pervasi...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
1 The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requireme...