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» Correct Execution of Reconfiguration for Stateful Components
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FORTE
1994
13 years 9 months ago
An improvement in formal verification
Critical safety and liveness properties of a concurrent system can often be proven with the help of a reachability analysis of a finite state model. This type of analysis is usual...
Gerard J. Holzmann, Doron Peled
ENTCS
2006
97views more  ENTCS 2006»
13 years 7 months ago
VyrdMC: Driving Runtime Refinement Checking with Model Checkers
This paper presents VyrdMC, a runtime verification tool we are building for concurrent software components. The correctness criterion checked by VyrdMC is refinement: Each executi...
Tayfun Elmas, Serdar Tasiran
FUIN
2008
119views more  FUIN 2008»
13 years 7 months ago
Modeling Communication with Synchronized Environments
A deterministic behavior of systems composed of several modules is a desirable design goal. Assembling a complex system from components requires also a high degree of re-usability....
Tiberiu Seceleanu, Axel Jantsch
RTCSA
1999
IEEE
13 years 12 months ago
A Symbolic Model Checker for Testing ASTRAL Real-Time Specifications
ASTRAL is a high-level formal specification language for real-time (infinite state) systems. It is provided with structuring mechanisms that allow one to build modularized specifi...
Zhe Dang, Richard A. Kemmerer
SAC
2010
ACM
14 years 23 days ago
An algorithm to generate the context-sensitive synchronized control flow graph
The verification of industrial systems specified with CSP often implies the analysis of many concurrent and synchronized components. The cost associated to these analyses is usu...
Marisa Llorens, Javier Oliver, Josep Silva, Salvad...