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» Correct Performance of Transaction Capabilities
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CODES
2009
IEEE
14 years 20 days ago
Native MPSoC co-simulation environment for software performance estimation
Performance estimation of Multi-Processor System-On-Chip (MPa high abstraction level is required in order to perform early architecture exploration and accurate design validations...
Patrice Gerin, Mian Muhammad Hamayun, Fréd&...
VLDB
2007
ACM
106views Database» more  VLDB 2007»
14 years 2 months ago
Why You Should Run TPC-DS: A Workload Analysis
The Transaction Processing Performance Council (TPC) is completing development of TPC-DS, a new generation industry standard decision support benchmark. The TPC-DS benchmark, firs...
Meikel Pöss, Raghunath Othayoth Nambiar, Davi...
APLAS
2008
ACM
13 years 10 months ago
Certified Reasoning in Memory Hierarchies
Abstract. Parallel programming is rapidly gaining importance as a vector to develop high performance applications that exploit the improved capabilities of modern computer architec...
Gilles Barthe, César Kunz, Jorge Luis Sacch...
AAAI
1996
13 years 9 months ago
Supporting Performance and Configuration Management of GTE Cellular Networks
GTE Laboratories, in cooperation with GTE Mobilnet, has developed and deployed PERFFEX (PERFormance Expert), an intelligent system for performance and configuration management of ...
Ming Tan, Carol Lafond, Gabriel Jakobson, Gary You...
CORR
2008
Springer
117views Education» more  CORR 2008»
13 years 7 months ago
Low-Complexity LDPC Codes with Near-Optimum Performance over the BEC
Recent works showed how low-density parity-check (LDPC) erasure correcting codes, under maximum likelihood (ML) decoding, are capable of tightly approaching the performance of an i...
Enrico Paolini, Gianluigi Liva, Michela Varrella, ...