1477 search results - page 159 / 296 » Criteria for the evaluation of implemented architectures |
IPPS
2006
IEEE
14 years 4 months ago
2006
IEEE
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
ANCS
2005
ACM
14 years 3 months ago
2005
ACM
This paper investigates the suitability of emerging tiled-architectures, equipped with low-latency on-chip networks, for high-performance network routing. In this paper, we presen...
EMSOFT
2004
Springer
14 years 3 months ago
2004
Springer
Dataflow synchronous languages have attracted considerable interest in domains such as real-time control and hardware design. The potential benefits are promising: Discrete-time...
WCW
2004
Springer
14 years 3 months ago
2004
Springer
Abstract. A wide range of techniques have been proposed, implemented, and even standardized for improving the performance of Web content delivery. However, previous work has found ...
INFOCOM
2002
IEEE
14 years 3 months ago
2002
IEEE
- This paper describes new optical switching architectures supporting asynchronous variable-length packets. Output line contention is resolved by optical delay line buffers. By int...