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ICS
2009
Tsinghua U.
14 years 2 months ago
Parametric multi-level tiling of imperfectly nested loops
Tiling is a crucial loop transformation for generating high performance code on modern architectures. Efficient generation of multilevel tiled code is essential for maximizing da...
Albert Hartono, Muthu Manikandan Baskaran, C&eacut...
ICS
2009
Tsinghua U.
14 years 2 months ago
Dynamic topology aware load balancing algorithms for molecular dynamics applications
Molecular Dynamics applications enhance our understanding of biological phenomena through bio-molecular simulations. Large-scale parallelization of MD simulations is challenging b...
Abhinav Bhatele, Laxmikant V. Kalé, Sameer ...
CCGRID
2008
IEEE
14 years 2 months ago
Scheduling Asymmetric Parallelism on a PlayStation3 Cluster
Understanding the potential and implications of asymmetric multi-core processors for cluster computing is necessary, as these processors are rapidly becoming mainstream components...
Filip Blagojevic, Matthew Curtis-Maury, Jae-Seung ...
CLUSTER
2003
IEEE
14 years 1 months ago
Implications of a PIM Architectural Model for MPI
Memory may be the only system component that is more commoditized than a microprocessor. To simultaneously exploit this and address the impending memory wall, processing in memory...
Arun Rodrigues, Richard C. Murphy, Peter M. Kogge,...
24
Voted
SRDS
2003
IEEE
14 years 1 months ago
Performance and Effectiveness Analysis of Checkpointing in Mobile Environments
Many mathematical models have been proposed to evaluate the execution performance of an application with and without checkpointing in the presence of failures. They assume that th...
Xinyu Chen, Michael R. Lyu