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MICRO
2005
IEEE
140views Hardware» more  MICRO 2005»
14 years 2 months ago
Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor
Data prefetching via helper threading has been extensively investigated on Simultaneous MultiThreading (SMT) or Virtual Multi-Threading (VMT) architectures. Although reportedly la...
Jiwei Lu, Abhinav Das, Wei-Chung Hsu, Khoa Nguyen,...
EUROPAR
2007
Springer
14 years 1 months ago
An Evaluation of Parallelization Concepts for Baseline-Profile Compliant H.264/AVC Decoders
Due to the increasing performance requirements of decoding H.264/AVC in HDTV or larger resolutions, new approaches are necessary to enable real-time processing. According to the cu...
Klaus Schöffmann, Markus Fauster, Oliver Lamp...
ISCA
2012
IEEE
262views Hardware» more  ISCA 2012»
11 years 11 months ago
Boosting mobile GPU performance with a decoupled access/execute fragment processor
Smartphones represent one of the fastest growing markets, providing significant hardware/software improvements every few months. However, supporting these capabilities reduces the...
Jose-Maria Arnau, Joan-Manuel Parcerisa, Polychron...
IPPS
2010
IEEE
13 years 7 months ago
A lock-free, cache-efficient multi-core synchronization mechanism for line-rate network traffic monitoring
Line-rate data traffic monitoring in high-speed networks is essential for network management. To satisfy the line-rate requirement, one can leverage multi-core architectures to par...
Patrick P. C. Lee, Tian Bu, Girish P. Chandranmeno...
SIGARCH
2008
97views more  SIGARCH 2008»
13 years 9 months ago
SP-NUCA: a cost effective dynamic non-uniform cache architecture
1 This paper presents a simple but effective method to reduce on-chip access latency and improve core isolation in CMP Non-Uniform Cache Architectures (NUCA). The paper introduces ...
Javier Merino, Valentin Puente, Pablo Prieto, Jos&...