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» Data exchange: computing cores in polynomial time
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WSC
1997
13 years 8 months ago
Design and Implementation of HLA Time Management in the RTI Version F.0
The DoD High Level architecture (HLA) has recently become the required method for the interconnection of all DoD computer simulations. The HLA addresses the rules by which simulat...
Christopher D. Carothers, Richard Fujimoto, Richar...
WADS
1995
Springer
82views Algorithms» more  WADS 1995»
13 years 10 months ago
On the Computation of Fast Data Transmissions in Networks with Capacities and Delays
We examine the problem of transmitting in minimum time a given amount of data between a source and a destination in a network with finite channel capacities and non–zero propaga...
Dimitrios Kagaris, Spyros Tragoudas, Grammati E. P...
IPPS
2005
IEEE
14 years 9 days ago
Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores
The use of pipelined floating-point arithmetic cores to create high-performance FPGA-based computational kernels has introduced a new class of problems that do not exist when usi...
Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna
AHS
2006
IEEE
142views Hardware» more  AHS 2006»
14 years 24 days ago
On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition
To increase the flexibility of single-chip evolvable hardware systems, we explore possibilities of systems with the evolutionary algorithm implemented in software on an onchip pr...
Kyrre Glette, Jim Torresen, Moritoshi Yasunaga, Yo...
APPT
2009
Springer
14 years 1 months ago
Computational Performance of a Parallelized Three-Dimensional High-Order Spectral Element Toolbox
In this paper, a comprehensive performance review of an MPI-based high-order three-dimensional spectral element method C++ toolbox is presented. The focus is put on the performance...
Christoph Bosshard, Roland Bouffanais, Christian C...