113 search results - page 13 / 23 » Data memory minimization by sharing large size buffers |
IPPS
2010
IEEE
13 years 5 months ago
2010
IEEE
Abstract--Ensuring the correctness of complex implementations of software transactional memory (STM) is a daunting task. Attempts have been made to formally verify STMs, but these ...
EUROPAR
2009
Springer
14 years 12 days ago
2009
Springer
The Cell Broadband Engine (Cell BE) is a heterogeneous multi-core processor specifically designed to exploit thread-level parallelism. Its memory model comprehends a common shared ...
INFOCOM
1992
IEEE
14 years 18 days ago
1992
IEEE
In order to take advantage of the low entry cost of the future public ATM (asynchronous transfer mode) network with shared facilities, it is highly desirable to interconnect diffe...
IPPS
1997
IEEE
14 years 22 days ago
1997
IEEE
This paper presents the design and evaluation of a multithreaded runtime library for parallel I/O. We extend the multi-threading concept to separate the compute and I/O tasks in t...
IPPS
2007
IEEE
14 years 2 months ago
2007
IEEE
Modern multi-core architectures have become popular because of the limitations of deep pipelines and heating and power concerns. Some of these multi-core architectures such as the...