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» Data parallel FPGA workloads: Software versus hardware
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122
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ASAP
2008
IEEE
82views Hardware» more  ASAP 2008»
15 years 10 months ago
Run-time thread sorting to expose data-level parallelism
We address the problem of data parallel processing for computational quantum chemistry (CQC). CQC is a computationally demanding tool to study the electronic structure of molecule...
Tirath Ramdas, Gregory K. Egan, David Abramson, Ki...
146
Voted
IPPS
2003
IEEE
15 years 8 months ago
Leveraging Block Decisions and Aggregation in the ShareStreams QoS Architecture
ShareStreams (Scalable Hardware Architectures for Stream Schedulers) is a canonical architecture for realizing a range of scheduling disciplines. This paper discusses the design c...
Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten ...
TCAD
2002
146views more  TCAD 2002»
15 years 3 months ago
Static scheduling of multidomain circuits for fast functional verification
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
Murali Kudlugi, Russell Tessier
DEBS
2010
ACM
15 years 6 months ago
Workload characterization for operator-based distributed stream processing applications
Operator-based programming languages provide an effective development model for large scale stream processing applications. A stream processing application consists of many runtim...
Xiaolan J. Zhang, Sujay Parekh, Bugra Gedik, Henri...
136
Voted
ERSA
2006
133views Hardware» more  ERSA 2006»
15 years 4 months ago
An FPGA based Co-Design Architecture for MIMO Lattice Decoders
MIMO systems have attracted great attentions because of their huge capacity. The hardware implementation of MIMO decoder becomes a challenging task as the complexity of the MIMO sy...
Cao Liang, Jing Ma, Xin-Ming Huang