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» Data partitioning on chip multiprocessors
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ASAP
2005
IEEE
182views Hardware» more  ASAP 2005»
14 years 3 months ago
A Thread and Data-Parallel MPEG-4 Video Encoder for a System-On-Chip Multiprocessor
We studied the dynamic instruction count reduction for a single-thread, vectorized and a multi-threaded, non-vectorized, MPEG-4 video encoder. Results indicate a maximum improveme...
Tom R. Jacobs, José L. Núñez-...
ASAP
2006
IEEE
130views Hardware» more  ASAP 2006»
14 years 3 months ago
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip
Data-Pipelining is a widely used model to represent streaming applications. Incremental decomposition and optimization of a data-pipelining application onto a multi-processor plat...
Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, ...
EMSOFT
2005
Springer
14 years 3 months ago
Optimizing inter-processor data locality on embedded chip multiprocessors
Recent research in embedded computing indicates that packing multiple processor cores on the same die is an effective way of utilizing the ever-increasing number of transistors. T...
Guilin Chen, Mahmut T. Kandemir
ICS
2011
Tsinghua U.
13 years 1 months ago
Predictive coordination of multiple on-chip resources for chip multiprocessors
Efficient on-chip resource management is crucial for Chip Multiprocessors (CMP) to achieve high resource utilization and enforce system-level performance objectives. Existing mul...
Jian Chen, Lizy Kurian John
ISCAS
2007
IEEE
123views Hardware» more  ISCAS 2007»
14 years 4 months ago
Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs
— This paper presents performance and area evaluation of a homogeneous multiprocessor communication system based on network-on-chip (NoC) in FPGA platforms. Two homogenous chip m...
Henrique C. Freitas, Dalton M. Colombo, Fernanda L...