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» Data-Flow Frameworks for Worst-Case Execution Time Analysis
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FPGA
2004
ACM
119views FPGA» more  FPGA 2004»
14 years 1 months ago
A quantitative analysis of the speedup factors of FPGAs over processors
The speedup over a microprocessor that can be achieved by implementing some programs on an FPGA has been extensively reported. This paper presents an analysis, both quantitative a...
Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vis...
IPPS
2005
IEEE
14 years 1 months ago
Fault-Tolerant Parallel Applications with Dynamic Parallel Schedules
Commodity computer clusters are often composed of hundreds of computing nodes. These generally off-the-shelf systems are not designed for high reliability. Node failures therefore...
Sebastian Gerlach, Roger D. Hersch
MASCOTS
2010
13 years 9 months ago
Efficient Discovery of Loop Nests in Execution Traces
Execution and communication traces are central to performance modeling and analysis. Since the traces can be very long, meaningful compression and extraction of representative beha...
Qiang Xu, Jaspal Subhlok, Nathaniel Hammen
PLDI
2000
ACM
14 years 18 hour ago
A framework for interprocedural optimization in the presence of dynamic class loading
Dynamic class loading during program execution in the JavaTM Programming Language is an impediment for generating code that is as e cient as code generated using static wholeprogr...
Vugranam C. Sreedhar, Michael G. Burke, Jong-Deok ...
PLDI
1990
ACM
13 years 11 months ago
A Fresh Look at Optimizing Array Bound Checking
- This paper describes techniques for optimizing range checks performed to detect array bound violations. In addition to the elimination of range check:s, the optimizations discuss...
Rajiv Gupta