260 search results - page 2 / 52 » Data-Layout Optimization Using Reuse Distance Distribution |
IEEEPACT
2009
IEEE
14 years 5 months ago
2009
IEEE
—With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bankinterleave...
CCGRID
2011
IEEE
13 years 2 months ago
2011
IEEE
Abstract—Parallel file systems are designed to mask the everincreasing gap between CPU and disk speeds via parallel I/O processing. While they have become an indispensable compo...
CC
2006
Springer
14 years 2 months ago
2006
Springer
Abstract. Profiling can effectively analyze program behavior and provide critical information for feedback-directed or dynamic optimizations. Based on memory profiling, reuse dista...
IEEEPACT
2006
IEEE
14 years 4 months ago
2006
IEEE
On machines with high-performance processors, the memory system continues to be a performance bottleneck. Compilers insert prefetch operations and reorder data accesses to improve...
IEEEPACT
1998
IEEE
14 years 3 months ago
1998
IEEE
Global locality analysis is a technique for improving the cache performance of a sequence of loop nests through a combination of loop and data layout optimizations. Pure loop tran...