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» Defect Avoidance in a 3-D Heterogeneous Sensor
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DFT
2004
IEEE
174views VLSI» more  DFT 2004»
13 years 10 months ago
Defect Avoidance in a 3-D Heterogeneous Sensor
A 3D Heterogeneous Sensor using a stacked chip is investigated. Optical Active Pixel Sensor and IR Bolometer detectors are combined to create a multispectral pixel for aligned col...
Glenn H. Chapman, Vijay K. Jain, Shekhar Bhansali
DFT
2005
IEEE
178views VLSI» more  DFT 2005»
14 years 20 days ago
Inter-Plane Via Defect Detection Using the Sensor Plane in 3-D Heterogeneous Sensor Systems
Defect and fault tolerance is being studied in a 3D Heterogeneous Sensor using a stacked chip with sensors located on the top plane, and inter-plane vias connecting these to other...
Glenn H. Chapman, Vijay K. Jain, Shekhar Bhansali
DFT
2006
IEEE
143views VLSI» more  DFT 2006»
14 years 1 months ago
Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC
This paper1 discusses a defect tolerant and energy economized computing array for the DSP plane of a 3-D Heterogeneous System on a Chip. We present the J-platform, which employs c...
Vijay K. Jain, Glenn H. Chapman