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CAV
1998
Springer
175views Hardware» more  CAV 1998»
14 years 1 months ago
An ACL2 Proof of Write Invalidate Cache Coherence
As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its...
J. Strother Moore
TVLSI
2008
126views more  TVLSI 2008»
13 years 9 months ago
Body Bias Voltage Computations for Process and Temperature Compensation
With continued scaling into the sub-90nm regime, the role of process, voltage and temperature (PVT) variations on the performance of VLSI circuits has become extremely important. T...
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatneka...
CACM
2011
134views more  CACM 2011»
13 years 1 months ago
Brain-computer interfaces for communication and control
For many years people have speculated that electroencephalographic activity or other electrophysiological measures of brain function might provide a new non-muscular channel for s...
Dennis J. McFarland, Jonathan R. Wolpaw
SENSYS
2009
ACM
14 years 4 months ago
Run time assurance of application-level requirements in wireless sensor networks
Continuous and reliable operation of WSNs is notoriously difficult to guarantee due to hardware degradation and environmental changes. In this paper, we propose and demonstrate a ...
Jingyuan Li, Yafeng Wu, Krasimira Kapitanova, John...
QI
2009
Springer
117views Physics» more  QI 2009»
14 years 4 months ago
Generalising Unitary Time Evolution
In this third Quantum Interaction (QI) meeting it is time to examine our failures. One of the weakest elements of QI as a field, arises in its continuing lack of models displaying...
Kirsty Kitto, Peter Bruza, Laurianne Sitbon