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» Deriving test plans from architectural descriptions
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ISLPED
1996
ACM
81views Hardware» more  ISLPED 1996»
14 years 2 months ago
Simulation based architectural power estimation for PLA-based controllers
We present an architectural power simulation technique for PLA-based controllers. The contributions of this work are (1) a simple but ecient power characterization of PLAs; and (2...
Srinivas Katkoori, Ranga Vemuri
STAIRS
2008
143views Education» more  STAIRS 2008»
13 years 11 months ago
Domain-Dependent View of Multiple Robots Path Planning
We study a problem of path planning for a group of robots in this paper. The problem is stated as a finding of spatial-temporal paths through which the robots can go from their ini...
Pavel Surynek
ETS
2010
IEEE
174views Hardware» more  ETS 2010»
13 years 11 months ago
Test-architecture optimization for TSV-based 3D stacked ICs
Testing of 3D stacked ICs (SICs) is becoming increasingly important in the semiconductor industry. In this paper, we address the problem of test architecture optimization for 3D s...
Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakr...
PDIS
1996
IEEE
14 years 2 months ago
Capabilities-Based Query Rewriting in Mediator Systems
Users today are struggling to integrate a broad range of information sources providing di erent levels of query capabilities. Currently, data sources with di erent and limitedcapa...
Yannis Papakonstantinou, Ashish Gupta, Laura M. Ha...
DAC
1996
ACM
14 years 2 months ago
Pseudorandom-Pattern Test Resistance in High-Performance DSP Datapaths
The testability of basic DSP datapath structures using pseudorandom built-in self-test techniques is examined. The addition of variance mismatched signals is identified as a testi...
Laurence Goodby, Alex Orailoglu