Sciweavers

1435 search results - page 225 / 287
» Description Logics
Sort
View
ISCAS
2003
IEEE
118views Hardware» more  ISCAS 2003»
14 years 3 months ago
SoC design integration by using automatic interconnection rectification
the interconnection among the IP cores with all description levels This paper presents an automatic interconnection rectification (AIR)technique to correct the misplaced interconne...
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
FPL
2009
Springer
91views Hardware» more  FPL 2009»
14 years 2 months ago
Large multipliers with fewer DSP blocks
Recent computing-oriented FPGAs feature DSP blocks including small embedded multipliers. A large integer multiplier, for instance for a double-precision floating-point multiplier...
Florent de Dinechin, Bogdan Pasca
WCRE
2000
IEEE
14 years 2 months ago
Next Generation Data Interchange: Tool-to-Tool Application Program Interfaces
Data interchange in the form of a standard exchange format(SEF) is only a first step towards tool interoperability. Inter-tool communication using files is slow and cumbersome; a ...
Susan Elliott Sim
ECAI
2000
Springer
14 years 2 months ago
Turning High-Level Plans into Robot Programs in Uncertain Domains
The actions of a robot like lifting an object are often best thought of as low-level processes with uncertain outcome. A highlevel robot plan can be seen as a description of a task...
Henrik Grosskreutz, Gerhard Lakemeyer
VLSID
1999
IEEE
122views VLSI» more  VLSID 1999»
14 years 2 months ago
Formal Verification of an ARM Processor
This paper presents a detailed description of the application of a formal verification methodology to an ARM processor. The processor, a hybrid between the ARM7 and the StrongARM ...
Vishnu A. Patankar, Alok Jain, Randal E. Bryant