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» Design For Testability Method for CML Digital Circuits
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VLSID
2005
IEEE
139views VLSI» more  VLSID 2005»
14 years 8 months ago
Variable Input Delay CMOS Logic for Low Power Design
Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
ICCAD
1994
IEEE
117views Hardware» more  ICCAD 1994»
13 years 11 months ago
Optimization of critical paths in circuits with level-sensitive latches
A simple extension of the critical path method is presented which allows more accurate optimization of circuits with level-sensitive latches. The extended formulation provides a s...
Timothy M. Burks, Karem A. Sakallah
ICCAD
2003
IEEE
193views Hardware» more  ICCAD 2003»
14 years 29 days ago
FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits
: This paper presents FROSTY, a computer program for automatically extracting the hierarchy of a large-scale digital CMOS circuit from its transistor-level netlist description and ...
Lei Yang, C.-J. Richard Shi
CVPR
2008
IEEE
13 years 9 months ago
Demosaicking recognition with applications in digital photo authentication based on a quadratic pixel correlation model
Most digital still color cameras use a single electronic sensor (CCD or CMOS) overlaid with a color filter array. At each pixel location only one color sample is taken, and the ot...
Yizhen Huang, Yangjing Long
TVLSI
2010
13 years 2 months ago
Computation Error Analysis in Digital Signal Processing Systems With Overscaled Supply Voltage
It has been recently demonstrated that digital signal processing systems may possibly leverage unconventional voltage overscaling (VOS) to reduce energy consumption while maintaini...
Yang Liu, Tong Zhang, Keshab K. Parhi