123 search results - page 1 / 25 » Design For Testability Method for CML Digital Circuits |
DATE
1999
IEEE
13 years 12 months ago
1999
IEEE
This paper presents a new Design for Testability (DFT) technique for Current-Mode Logic (CML) circuits. This new technique, with little overhead, using built-in detectors, monitor...
DSD
2008
IEEE
14 years 2 months ago
2008
IEEE
Testability is one of the most important factors that are considered during design cycle along with reliability, speed, power consumption, cost and other factors important for a c...
WCE
2007
13 years 8 months ago
2007
Improving testability during the early stages of High-level synthesis has several advantages including reduced test hardware overhead and design iterations. Recently, BIST techniq...
21
Voted
ISCAS
2003
IEEE
14 years 28 days ago
2003
IEEE
Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs, reduced design iter...
INTEGRATION
2006
13 years 7 months ago
2006
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...