123 search results - page 5 / 25 » Design For Testability Method for CML Digital Circuits |
ISMVL
2006
IEEE
14 years 1 months ago
2006
IEEE
Multiple-valued logic can be viewed as an alternative approach to solving many problems in transmission, storage, and processing of large and even increasing amounts of informatio...
ITC
2002
IEEE
14 years 18 days ago
2002
IEEE
Efficient production testing is frequently hampered because current digital circuits require test sets which are too large. These test sets can be reduced significantly by means...
TVLSI
2002
13 years 7 months ago
2002
Gate diffusion input (GDI)--a new technique of low-power digital combinatorial circuit design--is described. This technique allows reducing power consumption, propagation delay, an...
ATS
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper, we propose an oscillation-based test methodology for sequential testing. This approach provides many advantages over traditional methods. (1) It is at-speed testing...
ARVLSI
1999
IEEE
13 years 12 months ago
1999
IEEE
We describe a method to clock the domino pipeline at the maximum rate by using soft synchronizers between pipeline stages and thus allowing "time borrowing," i.e., allow...