123 search results - page 6 / 25 » Design For Testability Method for CML Digital Circuits |
DFT
2002
IEEE
14 years 19 days ago
2002
IEEE
Concurrent error detection (CED) methods are typically employed to provide an indication of the operational health of synchronous circuits during normal functionality. Existing CE...
CSREAESA
2003
13 years 9 months ago
2003
The paper presents a technique for the design of digital circuits based on reusable hardware templates (HT). Any HT is being constructed in such a way that it might be employed for...
AHS
2006
IEEE
13 years 9 months ago
2006
IEEE
The objective of this paper is to classify the approaches proposed to the evolutionary digital circuit design in the recent years and to identify the levels of complexity and inno...
IOLTS
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity p...
DSD
2010
IEEE
13 years 7 months ago
2010
IEEE
Abstract—Continuously shrinking feature sizes cause an increasing vulnerability of digital circuits. Manufacturing failures and transient faults may tamper the functionality. Aut...