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PDPTA
2003
13 years 9 months ago
Quaternary Arithmetic Logic Unit on a Programmable Logic Device
Common binary arithmetic operations such as addition/subtraction and multiplication suffer from O(n) carry propagation delay where n is the number of digits. Carry lookahead helps...
Songpol Ongwattanakul, Phaisit Chewputtanagul, Dav...
CSREAESA
2003
13 years 9 months ago
Common Mistakes in Adiabatic Logic Design and How to Avoid Them
Most so-called “adiabatic” digital logic circuit families reported in the low-power design literature are actually not truly adiabatic, in that they do not satisfy the general...
Michael P. Frank
CASES
2008
ACM
13 years 9 months ago
Active control and digital rights management of integrated circuit IP cores
We introduce the first approach that can actively control multiple hardware intellectual property (IP) cores used in an integrated circuit (IC). The IP rights owner(s) can remotel...
Yousra Alkabani, Farinaz Koushanfar
GLVLSI
2007
IEEE
194views VLSI» more  GLVLSI 2007»
13 years 11 months ago
Probabilistic maximum error modeling for unreliable logic circuits
Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate f...
Karthikeyan Lingasubramanian, Sanjukta Bhanja
JCIT
2008
144views more  JCIT 2008»
13 years 7 months ago
Design Methodology of a Controller to Forecast the Uncertain Cardiac Arrest Using Fuzzy Logic Approach
The main objective of design methodology of a controller for forecasting cardiac arrest using fuzzy logic approach is to provide the prediction of period of life time for the pati...
Nalayini Natarajan, Wahida Banu