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» Design Patterns for Reconfigurable Computing
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FPL
2008
Springer
116views Hardware» more  FPL 2008»
13 years 9 months ago
NOC architecture design for multi-cluster chips
For the next generation of multi-core processors, the onchip interconnection networks must be efficient to achieve high data throughput and performance. Moreover, these interconne...
Henrique C. Freitas, Philippe Olivier Alexandre Na...
TVLSI
2008
133views more  TVLSI 2008»
13 years 7 months ago
A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...
Mitchell J. Myjak, José G. Delgado-Frias
COMPSAC
2004
IEEE
13 years 11 months ago
Services-Oriented Dynamic Reconfiguration Framework for Dependable Distributed Computing
Web services (WS) received significant attention recently because services can be searched, bound, and executed at runtime over the Internet. This paper proposes a dynamic reconfi...
Wei-Tek Tsai, Weiwei Song, Raymond A. Paul, Zhibin...
FPGA
2004
ACM
163views FPGA» more  FPGA 2004»
13 years 11 months ago
Time and area efficient pattern matching on FPGAs
Pattern matching for network security and intrusion detection demands exceptionally high performance. Much work has been done in this field, and yet there is still significant roo...
Zachary K. Baker, Viktor K. Prasanna
VLSISP
2011
358views Database» more  VLSISP 2011»
13 years 2 months ago
Accelerating Machine-Learning Algorithms on FPGAs using Pattern-Based Decomposition
Machine-learning algorithms are employed in a wide variety of applications to extract useful information from data sets, and many are known to suffer from superlinear increases in ...
Karthik Nagarajan, Brian Holland, Alan D. George, ...