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» Design Recovery of a Two Level System
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VLSID
2008
IEEE
138views VLSI» more  VLSID 2008»
16 years 6 months ago
Memory Architecture Exploration Framework for Cache Based Embedded SOC
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
180
Voted
EUROPAR
2006
Springer
15 years 10 months ago
Hierarchical Model Validation of Symbolic Performance Models of Scientific Kernels
Multi-resolution validation of hierarchical performance models of scientific applications is critical primarily for two reasons. First, the step-by-step validation determines the c...
Sadaf R. Alam, Jeffrey S. Vetter
HPDC
1998
IEEE
15 years 10 months ago
Strings: A High-Performance Distributed Shared Memory for Symmetrical Multiprocessor Clusters
This paper introduces Strings, a high performance distributed shared memory system designed for clusters of symmetrical multiprocessors (SMPs). The distinguishing feature of this ...
Sumit Roy, Vipin Chaudhary
CASES
2001
ACM
15 years 10 months ago
Patchable instruction ROM architecture
Increased systems level integration has meant the movement of many traditionally off chip components onto a single chip including a processor, instruction storage, data path, and ...
Timothy Sherwood, Brad Calder
BMCBI
2008
126views more  BMCBI 2008»
15 years 6 months ago
ISOL@: an Italian SOLAnaceae genomics resource
Background: Present-day `-omics' technologies produce overwhelming amounts of data which include genome sequences, information on gene expression (transcripts and proteins) a...
Maria Luisa Chiusano, Nunzio D'Agostino, Alessandr...