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139
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CAI
2004
Springer
15 years 3 months ago
An Evolvable Combinational Unit for FPGAs
A complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evo...
Lukás Sekanina, Stepan Friedl
157
Voted
FPGA
2008
ACM
151views FPGA» more  FPGA 2008»
15 years 5 months ago
Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAs
Look-up table based FPGAs have migrated from a niche technology for design prototyping to a valuable end-product component and, in some cases, a replacement for general purpose pr...
Michael T. Frederick, Arun K. Somani
150
Voted
ASAP
2010
IEEE
171views Hardware» more  ASAP 2010»
15 years 3 months ago
General-purpose FPGA platform for efficient encryption and hashing
Many applications require protection of secret or sensitive information, from sensor nodes and embedded applications to large distributed systems. The confidentiality of data can b...
Jakub Szefer, Yu-Yuan Chen, Ruby B. Lee
FPGA
2008
ACM
136views FPGA» more  FPGA 2008»
15 years 5 months ago
HybridOS: runtime support for reconfigurable accelerators
We present HybridOS, a set of operating system extensions for supporting fine-grained reconfigurable accelerators integrated with general-purpose computing platforms. HybridOS spe...
John H. Kelm, Steven S. Lumetta
134
Voted
FPGA
2000
ACM
120views FPGA» more  FPGA 2000»
15 years 7 months ago
A novel high throughput reconfigurable FPGA architecture
With increased logic density due to the shift towards Deep Submicron technologies (DSM), FPGAs have become a viable option for implementing large designs. However, most commercial...
Amit Singh, Luca Macchiarulo, Arindam Mukherjee, M...