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Publication
_2011.jpg "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision")
In this paper we present a scalable dataflow hard- ware architecture optimized for the computation of general- purpose vision algorithms—neuFlow—and a dataflow compiler—luaFl...
JSW
2008
13 years 9 months ago
2008
Dynamic system reconfiguration techniques are presented that can enable the systematic evolution of software systems due to unanticipated changes in specification or requirements. ...
HPCA
2009
IEEE
14 years 9 months ago
2009
IEEE
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
ISCOPE
1998
Springer
14 years 1 months ago
1998
Springer
Metacomputing frameworks have received renewed attention of late, fueled both by advances in hardware and networking, and by novel concepts such as computational grids. However the...
NOCS
2007
IEEE
14 years 3 months ago
2007
IEEE
— Microarchitecturally integrated on-chip networks, or micronets, are candidates to replace busses for processor component interconnect in future processor designs. For micronets...