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RSP
2005
IEEE
131views Control Systems» more  RSP 2005»
14 years 1 months ago
Models for Embedded Application Mapping onto NoCs: Timing Analysis
Networks-on-chip (NoCs) are an emergent communication infrastructure, which can be designed to deal with growing system complexity and technology evolution. The efficient use of N...
César A. M. Marcon, Márcio Eduardo K...
ENTCS
2006
163views more  ENTCS 2006»
13 years 7 months ago
Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC
In recent years several successful GALS realizations have been presented. The core of a GALS system is a locally synchronous island that is designed using industry standard synchr...
Frank K. Gürkaynak, Stephan Oetiker, Hubert K...
ISPA
2004
Springer
14 years 27 days ago
Cayley DHTs - A Group-Theoretic Framework for Analyzing DHTs Based on Cayley Graphs
Static DHT topologies influence important features of such DHTs such as scalability, communication load balancing, routing efficiency and fault tolerance. Nevertheless, it is co...
Changtao Qu, Wolfgang Nejdl, Matthias Kriesell
ISCAS
2005
IEEE
127views Hardware» more  ISCAS 2005»
14 years 1 months ago
Energy and latency evaluation of NoC topologies
Abstract — Mapping applications onto different networks-onchip (NoCs) topologies is done by mapping processing cores on local ports of routers considering requirements like laten...
Márcio Eduardo Kreutz, César A. M. M...
GECCO
2008
Springer
196views Optimization» more  GECCO 2008»
13 years 8 months ago
ADANN: automatic design of artificial neural networks
In this work an improvement of an initial approach to design Artificial Neural Networks to forecast Time Series is tackled, and the automatic process to design Artificial Neural N...
Juan Peralta, Germán Gutiérrez, Arac...