Sciweavers

615 search results - page 42 / 123
» Design and Implementation of Parallel Algorithms for Gene-Fi...
Sort
View
VLSID
1996
IEEE
119views VLSI» more  VLSID 1996»
13 years 12 months ago
Parallel simulated annealing strategies for VLSI cell placement
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process, and as a result several research efforts have been un...
John A. Chandy, Prithviraj Banerjee
SIGCOMM
2009
ACM
14 years 2 months ago
Optimizing the BSD routing system for parallel processing
The routing architecture of the original 4.4BSD [3] kernel has been deployed successfully without major design modification for over 15 years. In the unified routing architectur...
Qing Li, Kip Macy
ERSA
2006
133views Hardware» more  ERSA 2006»
13 years 9 months ago
An FPGA based Co-Design Architecture for MIMO Lattice Decoders
MIMO systems have attracted great attentions because of their huge capacity. The hardware implementation of MIMO decoder becomes a challenging task as the complexity of the MIMO sy...
Cao Liang, Jing Ma, Xin-Ming Huang
APPROX
2008
Springer
107views Algorithms» more  APPROX 2008»
13 years 9 months ago
A General Framework for Designing Approximation Schemes for Combinatorial Optimization Problems with Many Objectives Combined in
Abstract. In this paper, we propose a general framework for designing fully polynomial time approximation schemes for combinatorial optimization problems, in which more than one ob...
Shashi Mittal, Andreas S. Schulz
INFOSCALE
2006
ACM
14 years 1 months ago
A library of constructive skeletons for sequential style of parallel programming
Abstract— With the increasing popularity of parallel programming environments such as PC clusters, more and more sequential programmers, with little knowledge about parallel arch...
Kiminori Matsuzaki, Hideya Iwasaki, Kento Emoto, Z...