615 search results - page 55 / 123 » Design and Implementation of Parallel Algorithms for Gene-Fi... |
IPPS
2003
IEEE
14 years 1 months ago
2003
IEEE
A software framework for the parallel execution of sequential programs using C++ classes is presented. The functional language Concurrent ML is used to implement the underlying ha...
ISCAS
2003
IEEE
14 years 1 months ago
2003
IEEE
A new vision chip, SCAMP-2, has been developed in a 0.35µm CMOS technology. In this paper, the design of the chip is presented, with particular emphasis on its readout architectu...
MSO
2003
13 years 9 months ago
2003
The use of sub-optimal digital systems can at times lead to high speed, efficient, costeffective structures that are sufficient to perform needed tasks. We describe here a system ...
STTT
2010
13 years 6 months ago
2010
Recent development in computer hardware has brought more wide-spread emergence of shared memory, multi-core systems. These architectures offer opportunities to speed up various ta...
ICIP
2007
IEEE
14 years 2 months ago
2007
IEEE
This paper presents some techniques for efficient motion estimation (ME) implementation on fixed-point digital signal processor (DSP) for high resolution video coding. First, chal...