47 search results - page 5 / 10 » Design and Implementation of Scalable Low-Power Montgomery M... |
GLVLSI
2002
IEEE
14 years 14 days ago
2002
IEEE
We present a low-power sine-output Direct Digital Frequency Synthesizer (DDFS) realized in 0.18 µm CMOS that achieves 60 dBc spectral purity from DC to the Nyquist frequency. No ...
GLVLSI
2003
IEEE
14 years 24 days ago
2003
IEEE
In this paper, we present a novel hybrid multiplier architecture that has the regularity of linear array multipliers and the performance of tree multipliers and is highly scalable...
ERSA
2006
13 years 9 months ago
2006
- This paper presents the design and implementation methodology of some low power programmable FIR filtering IP cores targeting SoRC and compares their performance in term of area,...
TVLSI
2010
13 years 2 months ago
2010
Mobile multimedia systems are growing in complexity, scalability and thus correspondingly in their implementation challenges. By design, these systems have built-in error resilienc...
VLSISP
1998
13 years 7 months ago
1998
This paper describes the architecture and the performance of a new programmable 16-bit Digital Signal Processor (DSP) engine. It is developed specifically for next generation wire...