1224 search results - page 146 / 245 » Design and Implementation of a Practical Parallel Delaunay A... |
128
click to vote
FPGA
2009
ACM
15 years 11 months ago
2009
ACM
This paper presents a hardware architecture for face detection based system on AdaBoost algorithm using Haar features. We describe the hardware design techniques including image s...
157
click to vote
ICIP
2009
IEEE
15 years 2 months ago
2009
IEEE
In this paper, we discuss the design of a highly-parallel motion estimator for real-time Scalable Video Coding (SVC). In an SVC, motion is commonly estimated bidirectionally and o...
119
click to vote
SPIN
2007
Springer
15 years 10 months ago
2007
Springer
Recent development in computer hardware has brought more wide-spread emergence of shared-memory, multi-core systems. These architectures offer opportunities to speed up various ta...
139
click to vote
PPOPP
2009
ACM
16 years 4 months ago
2009
ACM
Understanding why the performance of a multithreaded program does not improve linearly with the number of cores in a sharedmemory node populated with one or more multicore process...
119
click to vote
KDD
1997
ACM
15 years 8 months ago
1997
ACM
Many classification algorithms are designed to work with datasets that contain only discrete attributes. Discretization is the process of converting the continuous attributes of ...