1224 search results - page 181 / 245 » Design and Implementation of a Practical Parallel Delaunay A... |
113
Voted
IEEEPACT
2008
IEEE
15 years 10 months ago
2008
IEEE
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
157
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MASCOTS
2007
2007
A Novel Flow Control Scheme for Best Effort Traffic in NoC Based on Source Rate Utility Maximization
15 years 5 months ago
—Advances in semiconductor technology, has enabled designers to put complex, massively parallel multiprocessor systems on a single chip. Network on Chip (NoC) that supports high ...
161
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MIDDLEWARE
2005
Springer
15 years 9 months ago
2005
Springer
Distributed publish/subscribe systems are naturally suited for processing events in distributed systems. However, support for expressing patterns about disparate events and algorit...
166
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ICPPW
2007
IEEE
15 years 10 months ago
2007
IEEE
We study the role of task-level scheduling in power management on multicore multiple voltage embedded systems. Multicore on-achip, in particular DSP systems, can greatly improve p...
126
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JACM
2000
15 years 3 months ago
2000
We consider comparator networks M that are used repeatedly: while the output produced by M is not sorted, it is fed again into M. Sorting algorithms working in this way are called ...