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ISPASS
2007
IEEE
14 years 3 months ago
CA-RAM: A High-Performance Memory Substrate for Search-Intensive Applications
This paper proposes a specialized memory structure called CA-RAM (Content Addressable Random Access Memory) to accelerate search operations present in many important real-world ap...
Sangyeun Cho, Joel R. Martin, Ruibin Xu, Mohammad ...
ASPDAC
2006
ACM
178views Hardware» more  ASPDAC 2006»
14 years 2 months ago
Hardware architecture design of an H.264/AVC video codec
Abstract—H.264/AVC is the latest video coding standard. It significantly outperforms the previous video coding standards, but the extraordinary huge computation complexity and m...
Tung-Chien Chen, Chung-Jr Lian, Liang-Gee Chen
INFOCOM
2007
IEEE
14 years 3 months ago
Iterative Scheduling Algorithms
— The input-queued switch architecture is widely used in Internet routers due to its ability to run at very high line speeds. A central problem in designing an input-queued switc...
Mohsen Bayati, Balaji Prabhakar, Devavrat Shah, Ma...
IFIP
2010
Springer
14 years 24 days ago
Processing of Flow Accounting Data in Java: Framework Design and Performance Evaluation
Abstract Flow Accounting is a passive monitoring mechanism implemented in routers that gives insight into trac behavior and network characteristics. However, processing of Flow Ac...
Jochen Kögel, Sebastian Scholz
SPAA
2009
ACM
14 years 9 months ago
Brief announcement: selfishness in transactional memory
In order to be efficient with selfish programmers, a multicore transactional memory (TM) system must be designed such that it is compatible with good programming incentives (GPI),...
Raphael Eidenbenz, Roger Wattenhofer