164 search results - page 25 / 33 » Design and Implementation of the Memory Scheduler for the PC... |
IPPS
2009
IEEE
14 years 3 months ago
2009
IEEE
DTA (Decoupled Threaded Architecture) is designed to exploit fine/medium grained Thread Level Parallelism (TLP) by using a distributed hardware scheduling unit and relying on exi...
SIGCOMM
2006
ACM
14 years 2 months ago
2006
ACM
Many networking applications require fast state lookups in a concurrent state machine, which tracks the state of a large number of flows simultaneously. We consider the question ...
DAC
2005
ACM
14 years 9 months ago
2005
ACM
Partitioned BDD-based algorithms have been proposed in the literature to solve the memory explosion problem in BDD-based verification. Such algorithms can be at times ineffective ...
ASPLOS
2012
ACM
12 years 4 months ago
2012
ACM
Traditional storage systems provide a simple read/write interface, which is inadequate for low-locality update-intensive workloads because it limits the disk scheduling flexibili...
ISCA
2012
IEEE
11 years 11 months ago
2012
IEEE
Modern DRAMs have multiple banks to serve multiple memory requests in parallel. However, when two requests go to the same bank, they have to be served serially, exacerbating the h...