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» Design and Implementation of the TRIPS Primary Memory System
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ECRTS
2010
IEEE
13 years 8 months ago
Making DRAM Refresh Predictable
Embedded control systems with hard real-time constraints require that deadlines are met at all times or the system may malfunction with potentially catastrophic consequences. Sched...
Balasubramanya Bhat, Frank Mueller
EUROSYS
2011
ACM
12 years 11 months ago
SRM-buffer: an OS buffer management technique to prevent last level cache from thrashing in multicores
Buffer caches in operating systems keep active file blocks in memory to reduce disk accesses. Related studies have been focused on how to minimize buffer misses and the caused pe...
Xiaoning Ding, Kaibo Wang, Xiaodong Zhang
ICC
2007
IEEE
14 years 1 months ago
Towards Sender-Based TFRC
—Pervasive communications are increasingly sent over mobile devices and personal digital assistants. This trend has been observed during the last football world cup where cellula...
Guillaume Jourjon, Emmanuel Lochin, Patrick S&eacu...
ISORC
2002
IEEE
14 years 9 days ago
Integrating Real-Time Synchronization Schemes into Preemption Threshold Scheduling
Preemption threshold scheduling (PTS) provides prominent benefits for fixed priority scheduling such as increased schedulability, reduced context switches, and decreased memory re...
Saehwa Kim, Seongsoo Hong, Tae-Hyung Kim
PADS
1998
ACM
13 years 11 months ago
GloMoSim: A Library for Parallel Simulation of Large-Scale Wireless Networks
A number of library-based parallel and sequential network simulators have been designed. This paper describes a library, called GloMoSim (for Global Mobile system Simulator), for ...
Xiang Zeng, Rajive Bagrodia, Mario Gerla