529 search results - page 16 / 106 » Design and Test Space Exploration of Transport-Triggered Arc... |
DAC
2005
ACM
14 years 9 months ago
2005
ACM
Achieving design closure is one of the biggest headaches for modern VLSI designers. This problem is exacerbated by high-level design automation tools that ignore increasingly impo...
DATE
2010
IEEE
14 years 1 months ago
2010
IEEE
There is today little doubt on the fact that a high-performance and cost-effective Network-on-Chip can only be designed in 45nm and beyond under a relaxed synchronization assumpti...
FDL
2008
IEEE
14 years 3 months ago
2008
IEEE
The features of the emerging modeling languages for system design allow designers to build models of almost any kind of heterogeneous hardware-software systems, including Real Tim...
HPCA
2006
IEEE
14 years 9 months ago
2006
IEEE
This paper explores the multi-dimensional design space for chip multiprocessors, exploring the inter-related variables of core count, pipeline depth, superscalar width, L2 cache s...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...