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» Design and evaluation of an auto-memoization processor
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2005
IEEE
15 years 9 months ago
A pipelined data-parallel algorithm for ILP
The amount of data collected and stored in databases is growing considerably for almost all areas of human activity. Processing this amount of data is very expensive, both humanly...
Nuno A. Fonseca, Fernando M. A. Silva, Víto...
IPPS
2005
IEEE
15 years 9 months ago
Accelerating Scientific Applications with the SRC-6 Reconfigurable Computer: Methodologies and Analysis
Reconfigurable computing offers the promise of performing computations in hardware to increase performance and efficiency while retaining much of the flexibility of a software sol...
Melissa C. Smith, Jeffrey S. Vetter, Xuejun Liang
ISCAS
2005
IEEE
152views Hardware» more  ISCAS 2005»
15 years 9 months ago
Dictionary-based program compression on transport triggered architectures
— Program code size has become a critical design constraint of embedded systems. Large program codes require large memories, which increase the size and cost of the chip. Poor co...
Jari Heikkinen, Andrea G. M. Cilio, Jarmo Takala, ...
ITCC
2005
IEEE
15 years 9 months ago
On the Masking Countermeasure and Higher-Order Power Analysis Attacks
Abstract— Masking is a general method used to thwart Differential Power Analysis, in which all the intermediate data inside an implementation are XORed with random Boolean values...
François-Xavier Standaert, Eric Peeters, Je...
EUROPAR
2005
Springer
15 years 9 months ago
Non-uniform Instruction Scheduling
Dynamic instruction scheduling logic is one of the most critical and cycle-limiting structures in modern superscalar processors, and it is not easily pipelined without significant ...
Joseph J. Sharkey, Dmitry V. Ponomarev