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» Design and evaluation of an auto-memoization processor
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JEC
2006
88views more  JEC 2006»
13 years 7 months ago
Synchroscalar: Evaluation of an embedded, multi-core architecture for media applications
We present an overview of the Synchroscalar single-chip, multi-core processor. Through the design of Synchroscalar, we find that high energy efficiency and low complexity can be a...
John Oliver, Ravishankar Rao, Diana Franklin, Fred...
NOCS
2007
IEEE
14 years 1 months ago
Implementation and Evaluation of a Dynamically Routed Processor Operand Network
— Microarchitecturally integrated on-chip networks, or micronets, are candidates to replace busses for processor component interconnect in future processor designs. For micronets...
Paul Gratz, Karthikeyan Sankaralingam, Heather Han...
CASES
2008
ACM
13 years 9 months ago
VESPA: portable, scalable, and flexible FPGA-based vector processors
While soft processors are increasingly common in FPGAbased embedded systems, it remains a challenge to scale their performance. We propose extending soft processor instruction set...
Peter Yiannacouras, J. Gregory Steffan, Jonathan R...
JIRS
2007
229views more  JIRS 2007»
13 years 7 months ago
Unmanned Vehicle Controller Design, Evaluation and Implementation: From MATLAB to Printed Circuit Board
A detailed step-by-step approach is presented to optimize, standardize, and automate the process of unmanned vehicle controller design, evaluation, validation and verification, fol...
Daniel Ernst, Kimon P. Valavanis, Richard Garcia, ...
CORR
2007
Springer
111views Education» more  CORR 2007»
13 years 7 months ago
Comments on "Design and performance evaluation of load distribution strategies for multiple loads on heterogeneous linear daisy
Min, Veeravalli, and Barlas have proposed strategies to minimize the overall execution time of one or several divisible loads on a heterogeneous linear network, using one or more ...
Matthieu Gallet, Yves Robert, Frédér...