584 search results - page 104 / 117 » Design and implementation of correlating caches |
128
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ISCA
2007
IEEE
15 years 10 months ago
2007
IEEE
Store misses cause significant delays in shared-memory multiprocessors because of limited store buffering and ordering constraints required for proper synchronization. Today, prog...
177
Voted
PPOPP
2006
ACM
15 years 10 months ago
2006
ACM
Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed t...
141
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SPAA
2003
ACM
15 years 9 months ago
2003
ACM
We propose a new approach for constructing P2P networks based on a dynamic decomposition of a continuous space into cells corresponding to servers. We demonstrate the power of thi...
153
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IEEEPACT
2002
IEEE
15 years 9 months ago
2002
IEEE
Simultaneous Multithreading (SMT) processors achieve high processor throughput at the expense of single-thread performance. This paper investigates resource allocation policies fo...
142
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EMSOFT
2006
Springer
15 years 7 months ago
2006
Springer
Upper bounds on worst-case execution times, which are commonly called WCET, are a prerequisite for validating the temporal correctness of tasks in a real-time system. Due to the e...